1. Field of the Invention
The present invention relates to a driver, and more particularity, to a data driver for a liquid crystal display.
2. Discussion of the Related Art
Referring to FIG. 1, a general active matrix liquid crystal display includes a lower substrate on which gate lines G1-Gn, data lines D1-Dn, a thin film transistor for switching pixels, and a pixel electrode are arranged. An upper substrate has a color filter for displaying colors and a common electrode. A liquid crystal panel 1 has a liquid crystal filled between the two upper and lower substrates, and a gate driver 2 sequentially applies driving signals to respective gate lines G1-Gn of liquid crystal panel 1. A data driver 3 applies video data to respective data lines D1-Dn of liquid crystal panel 1.
In such a liquid crystal display, liquid crystal panel 1 is becoming larger and with higher resolution. In order to drive larger and higher-resolution liquid crystal displays, the driving frequency of respective drivers 2 and 3 becomes higher. However, it is difficult to develop a driver IC capable of directly driving such a high frequency. Even though the driver IC capable of directly driving the high frequency may be developed, direct driving is not feasible due to high-frequency EMI. For this reason, as shown in FIG. 2, a data driver is provided on both sides of liquid crystal panel 1 according to two separate even and odd lines so that the driving frequency is reduced by half.
In the liquid crystal display of FIG. 2, however, because the driver is formed on both sides, the area of the liquid crystal panel for displaying actual images becomes smaller in the overall liquid crystal display. This limits the obtaining of a large-sized screen. The data driver of the conventional liquid crystal display of FIG. 1 will be discussed with reference to FIG. 3.
The data driver of the conventional liquid crystal display includes an m-bit shift register 11 for shifting a source start pulse SSP by a source pulse clock SCL and outputting a latch clock. A data latch 12 latches and outputs three signals DA(n), DB(n), and DC(n) of display data by source clock SCL. A line conversion logic 14 converts the polarity for every horizontal period by an external POL signal for the purpose of inversion. A 3m-by-n-bit two-line latch 13 latches, by lines, all display data of one horizontal line output from data latch 12 by the latch clock output from shift register 11 according to an external load signal and the output of line conversion logic 14. A D/A converter 15 selects and outputs one voltage of 2.sup.n levels formed by an external reference voltage so as to convert the data output from line latch 13 into an analog signal to be applied to the liquid crystal. A data output circuit 16 amplifies the signal output from D/A converter 15 to a stable voltage having a sufficient driving capability and a less-deviation output voltage. The amplified signal is output to the liquid crystal.
The operation of the conventional data driver will be described below with reference to FIG. 4. First, shift register 11 receives source clock SCL and source start pulse SSP, and outputs m latch clocks SR01, SR02, SR03, . . . , and SR0m (m=64) sequentially to line latch 13. Source clock SCL is a clock signal of about 65 MHz in XGA. The R/L input is a shift right/left input that informs the mBIT shift register 11 to shift right or left.
Data latch 12 latches signals DA(n), DB(n), and DC(n) of the n-bit display data corresponding to the falling edge of source clock SCL, and outputs the latched result to line latch 13. Line latch 13 latches the n-bit display data latched to the falling edge of the source clock to 3m-by-n bit first line latch portion 13a by latch clocks SR01, SR02, SR03, . . . , and SR0m output from shift register 11. After one horizontal line of display data is stored, one line data is stored in second line latch portion 13b at one time by an external load signal LOAD. Simultaneously, the next line data is latched to first line latch portion 13a by latch clocks SR01, SR02, SR03, . . . , and SR0m output from shift register 11 in the same method as above. This operation is performed repeatedly.
The line data stored by line latch 13 is output to D/A converter 15. D/A converter 15 selects and outputs, from the 2.sup.n levels formed by an external reference voltage v.sub.REP in an internal decoder, one voltage corresponding to the line data input from line latch 13. Here, line conversion logic 14 converts the polarity for every line by the external POL signal to facilitate the inversion.
The analog signal selected and output from D/A converter 15 is applied and displayed to the liquid crystal as a stable voltage having a sufficient driving capability and less-deviation output voltage. The conventional data driver, however, has the following drawbacks.
With the trend of larger screens and higher resolution, the hardest obstacle in the application of liquid crystal displays to liquid crystal laptop computers and their monitors is the operation frequency (65 MHz for XGA and 107 MHz for EWS) in accordance with resolution. The operation frequency of the conventional IC data driver is 55 MHz at 5 V driving (40 MHz at 3.3 V). Hence, the driver cannot be driven directly. Even when a directly drivable driver IC is developed, high frequency EMI is involved, making the direct driving impossible.
An external line memory may be provided in the conventional data driver in order to reduce frequency into half through bisected driving or driving by ICS. In this case, however, the cost as well as the weight of the product increase due to the line memory. Accordingly, power consumption and volume are also increased.